The present invention relates generally to cache organization in a multi-processor environment and more particularly to cache directory coherence.
In multi-processor information processing devices where multiple processing devices share a main storage device and each processing device is equipped with a cache storage module for storing a copy of a section of the main storage device, a coherence control device is generally provided to assure consistency (coherence) between the main storage device and the cache storage module equipped in each of the processing devices. The coherence control device is equipped with a cache directory for each of the processing devices. A cache directory is a copy of the address tags (cache tags) stored in the cache of the processing device. When another processing device performs a write operation to the main storage device, the processing device, other than the processing device performing the write, searches the cache directory. If an address tag matching the write address is registered in the directory, the corresponding entry in the cache storage module in the processing device is reported to be invalid.
FIG. 1 [PRIOR ART] shows an example of a configuration of a conventional cache directory. Here, a cache directory 1 is a copy of an address tag stored in the cache of a processing device. A coherence control device contains a cache directory 1 for each processing device. When the processing device performs a block transfer from the main storage device to the cache storage module and newly registers an address tag, the same address tag is registered by way of a cache directory registration address interface 3 in the cache directory 1 entry indicated by a read/write pointer 11 by way of a cache directory index interface 2. When a write is performed to the main storage device from another processing device, the contents of the cache directory indicated by the read/write pointer 11 is read by way of the cache directory index interface 2, and the contents are stored in a read register 12. A comparator 14 then compares the contents of the read register 12 with the contents of a store address register 13 stored by way of a store address interface 4. If there is a match, the processing device is notified that the cache entry is invalid by way of an interface 5.
The main storage device shared by the plurality of processing devices is generally formed as a bank of independently operable, distinct address spaces. The throughput with the processing devices is high. With recent demands for higher speeds, the cache directory also requires a throughput similar to that of the main storage device. However, in the conventional cache directory architecture shown in FIG. 1, the cache directory has only one read path. Thus, the cache directory can perform searches only one at a time and no throughput improvements can be provided.
In addition to the above problems, the cache storage modules of processing devices are getting larger and larger, hence providing high cache directory search performance requires greater hardware capacity. With the high cache capacity used in current information processing devices where multiple processing devices are connected together, the hardware requirements are significant. Thus, there is a need to keep hardware requirements low while providing high cache directory search performance.